Bringing Tiny Chiplets To Embedded SoCs
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LONDON — ZeroASIC has developed a technology platform to bring chiplets to embedded system design, as a time-efficient alternative to designing and manufacturing custom application-specific ICs (ASICs). The platform is based on swappable pre-fabbed 2 x 2 mm chiplets on an active silicon interposer, which customers can design for themselves in a matter of minutes using ZeroASIC’s online EDA tool.
The company’s aim is to reduce the barrier to making custom ASICs versus using off-the-shelf SoCs. ZeroASIC CEO Andreas Olofsson told EE Times that the biggest cost, in terms of both time and money, for custom ASICs is tapeouts.
“A tapeout might cost $10 million, and it takes 6 months to come out of the foundry,” he said. “So, if you want to make it faster, you clearly can’t have any tapeouts, and that’s where the chiplets come in.”
Working with pre-defined, pre-fabbed chiplets means that, provided they are in stock and there is OSAT capacity, a custom ASIC design made up of small chiplets can be produced in a matter of days, Olofsson said.
“[Companies working on reticle-sized chiplets] haven’t really solved the tapeout problem,” he said. “They’re still spending a lot of money—they’re improving yield and per-unit cost, but they aren’t leaving behind infrastructure they can use for next time. My thought is: these chiplets are really massive SoCs—5 billion transistors and 100 mm2. I thought that was wrong. I wanted to make something that sounded like a chiplet and was 1 or 2 mm in size.”
“If we can create this catalog of chiplets that are sitting on the shelf in die form and the only thing we have to do is use a pick and place machine to place them on an interposer, put the heat sink on and be done, we can be done in a week,” he said.
ZeroASIC intends to create a platform for the ‘long tail’—applications that are too niche for off-the-shelf SoCs. Olofsson names IoT and industrial robotics as target markets, where applications are fragmented and low-volume, but the total opportunity is large.
“Companies making chips for this market are struggling with cost, and if their markets are even a little bit smaller, they can’t afford to go after them,” he said. “So, they make platforms that may or may not have the features the customer wants, and if they do, they’re too expensive and power hungry.”
Will a chiplet platform with just a few types of chiplet be custom enough for these niches? Olofsson said that for edge intelligence, automotive and wireless base stations, for example, SoCs might only have a couple of blocks that are different.
“Chip companies have to try and guess what the market needs—they go and talk to customers, but the big ones will never tell you exactly what they need,” he said. “A lot of times you end up with a product that isn’t perfect…what if we let the market decide? Not decide for them what they need three years from now.”
Olofsson describes ZeroASIC’s concept as “the LSI Logic of silicon” (in the 1980s, LSI Logic’s gate arrays were fixed in silicon but customization of the interconnect layers could produce something analogous to an ASIC).
“The die size was fixed, so people were wasting a lot of money on die area [they didn’t need], but it worked out,” he said.
Chiplet design
ZeroASIC designed a mechanical and electrical standard for its tiny chiplets to make them swappable, including the interface, link layer, communication protocol and pin out. This standard, which Olofsson said the company will disclose soon, will be completely open.
ZeroASIC will develop a catalog of different types of chiplets in the same form factor, along with active interposers in several size choices. The eventual aim will be to open the ecosystem to other chiplet makers.
“It’s very hard to get people to invest that kind of money until you have a platform—for someone to design a chiplet into our ecosystem would cost them millions of dollars,” he said. “But once that happens, that’s a very good sign!”
In the mean time, ZeroASIC designed and prototyped three types of chiplet itself—a RISC-V CPU and an FPGA based on open-source projects, and an AI accelerator of its own design. The AI accelerator, while not state-of-the-art just yet, will continue to evolve, he said. I/O IP is licensed from a third party.
An active interposer—effectively a network-on-chip—is required to keep wires short and it makes for easier PHYs and simpler chiplets. This interposer will be available in several fixed sizes (small, medium, large, extra large). In terms of cost, Olofsson said that at the legacy nodes ZeroASIC will use for this interposer—likely 28 nm—the cost of the interposer becomes a small part of the total.
Currently, there isn’t a three-dimensional chiplet communication protocol—standards like UCIe and BoW are two-dimensional—so ZeroASIC has also had to come up with a protocol it calls C-Link for chiplet-to-chiplet communication via a 3D active interposer. Existing power-hungry standards are also not designed for the very short distances ZeroASIC’s chiplets need to communicate over, according to Olofsson.
“We had to come up with something that looked more like AXI, where it’s very tightly coupled, with less than 0.1 pico Joule per bit energy transfer cost,” he said.
At the edge of ZeroASIC’s interposer is UCIe, to allow communication onward to other UCIe-compatible chiplets.
Emulation tool
Most merchant silicon vendors rely on keeping gross margin up by shipping high volumes, Olofsson said, meaning NRE (non-recurring engineering cost—the cost of designing the chip) is insignificant. However, for small volumes, NRE dominates the cost.
To tackle NRE, ZeroASIC has created a no-code, cloud-based emulation platform, ChipMaker, which enables customers to drag and drop chiplets onto an interposer and then emulate the system on Amazon F1 instances. A software driver is created on the fly for the combination of chiplets the customer has selected so software can be tested. It also creates a datasheet for the new ASIC.
How hard will this be to maintain as the number of different types of chiplets available grows?
“If we stay with the rigid memory-mapped API, and the standard between them, as long as all the blocks are designed to the API, then [it will work],” Olofsson said. “All the chiplets we design use the same template—only the core logic changes, the periphery is the same.”
ChipMaker is designed for embedded systems engineers who are used to programming SoCs, but don’t want to be exposed to chip design problems like static timing analysis, IR drop or on-chip variability.
“Tapeouts, LVS, DRC, EDA tools: all gone,” Olofsson said. “So, in that respect it isn’t like chip design. It’s more like how someone would design a board today.”
ZeroASIC will be a fabless semiconductor company selling packaged devices made up of its chiplets in different combinations. Prior to 2020, the company was known as Adapteva and had been working on parallel processors since 2008. Olofsson left to run DARPA’s CHIPS (Common Heterogeneous Integration and IP Reuse Strategies) program for three years before rejoining in 2020 to refocus the company as ZeroASIC. Today, ZeroASIC is entirely funded by revenue from existing U.S. government contracts and employs 18 people in the U.S. and Europe.
This piece of article is written by Sally Ward-Foxton and published at https://www.eetimes.com/bringing-tiny-chiplets-to-embedded-socs/
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